Dynamically configurated storage array with improved data access

ABSTRACT

A reconfigurable memory having M bit lines and a plurality of row lines, where M&gt;1. The memory includes an array of memory storage cells, each memory storage cell storing a data value. The data value is read from or into the storage cells by coupling that data value to one of the bit lines in response to a row control signal on one of the row lines. A row select circuit generates the row control signal on one of the row lines in response to a row address being coupled to the row select circuit. The row select circuit includes a memory for storing a mapping of the row addresses to the row lines that determines which of the row lines is selected for each possible value of the row address. The memory includes a plurality of sense amplifiers, one such sense amplifier being connected to each of the bit lines for measuring a signal value on that bit line. A controller that is part of the memory tests the memory storage cells both at power up and run time to detect defective memory storage cells. The controller uses an error correcting code scheme to detect errors during the actual operation of the memory. The memory includes sufficient spare rows and columns to allow the controller to substitute spares for rows or columns having defective memory storage cells.

RELATED APPLICATIONS

[0001] This application is a continuation-in-part of U.S. patentapplication Ser. No. 09/580,936, filed May 25, 2000.

FIELD OF THE INVENTION

[0002] The present invention relates to memory systems, and moreparticularly, to a memory system, which detects errors and reconfiguresitself to avoid bad memory cells.

BACKGROUND OF THE INVENTION

[0003] As the cost of computational hardware has decreased, computerswith ever-larger memory systems have proliferated. Systems with hundredsof Mbytes are common, and systems with a few Gbytes of memory arecommercially available. As the size of the memory increases, problemsarising from bad memory cells become more common.

[0004] Memory failures may be divided into two categories, thoseresulting from bad memory cells that are detected at the time ofmanufacture and those that arise from cells that fail during theoperation of the memory. At present, problems arising from defectivememory cells that are detected during the manufacturing process arecured by replacing the bad cells. The typical memory array is dividedinto blocks. Each memory chip has a predetermined number of spare blocksfabricated thereon. If a block in the memory is found to have adefective memory cell, the block in question is disconnected from theappropriate bus and one of the spares is connected to the bus in itsplace. However, once the part is packaged, there is no means forreplacing a block with a spare, since the replacement process requireshard wiring of the spares to the bus.

[0005] The cost of testing the memory chips is a significant factor inthe cost of the chips. The rate at which memory cells can be tested islimited by the internal organization of the memory blocks and the speedof the buses that connect the memory blocks to the test equipment. Thevarious buses are limited to speeds of a few hundred MHz. Data istypically written and read as blocks having 64 bits or less. Since awrite operation followed by a read operation requires several clockcycles, the rate at which memory can be tested is limited to 100 milliontests per second. Extensive testing requires each memory cell to betested a large number of times under different conditions such astemperature and clock speed. Hence, a 1 Gbyte memory chip would requireminutes, if not hours, to thoroughly test. The cost of such testingwould be prohibitive; hence, prior art memory chip designs will notpermit extensive testing at the 1 Gbyte level and beyond.

[0006] Even when the obviously bad memory blocks have been removed,sooner or later, the memory will fail because of the failure of one ormore cells in a block. The probability that such a failure will cause asystem failure depends on the lifetime of the system, the size of thememory, and the type of memory. The probability of such a failureincreases with the lifetime of the system and the size of the memory.While system lifetimes are not increasing, the size of memory isincreasing. Accordingly, more system failures are expected.

[0007] In addition, some types of memory cells have higher failure ratesthan others. For example, EEPROM and flash memories can only be writtena relatively small number of times compared to conventional DRAM andstatic RAM memories. In the case of EEPROMs and flash memories, thelimited number of write cycles imposes severe restrictions on thepossible applications of these memories. Similarly, memories based onferroelectrics have relatively small lifetimes relative to theseconventional memories; however, the ferroelectric memories can bewritten many more times than EEPROMs and flash memories.

[0008] In principle, all of these types of memories would benefit byhaving some form of reconfiguration system built directly into thememory. Such a system would replace blocks of memory that fail duringthe operational life of the system, thereby extending the lifetime ofthe system. However, prior to a memory cell actually failing, there isoften a period of time in which the memory cell operates, but with ahigh error rate. Such a memory cell can cause intermittent systemfailures and may be very difficult to diagnose. Hence, any form of blockreplacement system that depends on detecting the failure of a block maynot be able to operate successfully.

[0009] Broadly, it is the object of the present invention to provide animproved memory system.

[0010] It is a further object of the present invention to provide amemory system that can be reconfigured after the parts have beenpackaged.

[0011] It is a still further object of the present invention to providea memory system that can detect memory cells with high error rates andreplace these cells prior to the error rates causing system failures.

[0012] These and other objects of the present invention will becomeapparent to those skilled in the art from the following detaileddescription of the invention and the accompanying drawings.

SUMMARY OF THE INVENTION

[0013] The present invention is a reconfigurable memory having M bitlines and a plurality of row lines, where M>1. The memory includes anarray of memory storage cells, each memory storage cell storing a datavalue. The data value is read from or into the storage cells by couplingthat data value to one of the bit lines in response to a row controlsignal on one of the row lines. A row select circuit generates the rowcontrol signal on one of the row lines in response to a row addressbeing coupled to the row select circuit. The row select circuit includesa memory for storing a mapping of the row addresses to the row linesthat determines which of the row lines is selected for each possiblevalue of the row address. The memory includes a plurality of senseamplifiers, one such sense amplifier being connected to each of the bitlines for measuring a signal value on that bit line. The memory includesa controller that tests the memory storage cells and eliminatesreferences to rows having defective storage cells from the row mapping.When the memory is powered up, the controller tests the memory cells andassigns row addresses in a manner that eliminates references in the rowmapping to rows having defective storage cells. In one embodiment of theinvention, the memory also includes a single cell memory for storing aplurality of single data values, each data value corresponding to one ofthe row addresses and one of the bit lines. An insertion circuit causesthat data value stored in the single cell memory for one of the rowaddresses and bit lines to replace that value stored in the memorystorage cell coupled to that bit line when that row address is coupledto the row select circuit. The memory also includes a word assemblycircuit for selecting N bit lines from said M bit lines, where N is lessthan or equal to M. The word assembly circuit includes a memory forstoring a mapping specifying the N bit lines for each possible rowaddress. In such embodiments, the controller alters the mapping toeliminate a reference in the mapping to a bit line that causes adefective storage cell to couple data to a bit line in response to oneof the row addresses. The memory also includes an error correctingcircuit for detecting errors in data words. The error correcting circuitgenerates a corrected data word and an error data word from the N datavalues coupled thereto, the error data word indicating which of the Ndata values, if any, was erroneous. The N data values are determined bya word assembly circuit that connects N of the M bit lines to the errorcorrecting circuit, where N is less than or equal to M. A controlcircuit connected to the error correcting circuit uses the error datawords and the row addresses to alter the mapping in the row selectcircuit in response to the error data words so as to avoid defectivememory storage cells or bit lines.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014]FIG. 1 is a block diagram of a memory 10 according to the presentinvention.

[0015]FIG. 2 is a block diagram of a memory 50 that utilizes an errorcorrecting codes according to the present invention.

[0016]FIG. 3 is a block diagram of a memory 100 constructed from aplurality of memory banks according to the present invention.

[0017]FIG. 4 is a block diagram of a memory according to anotherembodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0018] The manner in which the present invention gains its advantagescan be more easily understood with reference to FIG. 1 which is a blockdiagram of a memory 10 according to the present invention. For thepurposes of this discussion, it will be assumed that memory 10 storesdata words having ND bits per word. The data is stored in atwo-dimensional array 11 of memory cells that are organized into aplurality of rows and columns. A typical storage cell is shown at 15.All bits of any given data word are stored on the same row. The specificrow is determined by a mapping that is stored in a content addressablememory (CAM) 43 that stores a mapping of the logical addresses used bythe outside computer system to the row addresses used with memory 10.

[0019] In the preferred embodiment of the present invention, a number ofwords are stored in each row. A word is selected via a row selectcircuit 14 which causes the storage cells associated with that row to beconnected to a plurality of bit lines. Hence, by placing the appropriatesignal on line 13, storage cell 15 is connected to bit line 12. If datais to be written into the word, the data values are coupled to theappropriate bit lines via a cross-connect switch 20. If data is to beread from the word, the data values stored in the storage cells on theselected row are placed on the bit lines by the selected storage cellsand decoded by a block of sense amplifiers 21. The specific bit linescorresponding to the desired word are then selected by cross-connectswitch 23. The mapping of the physical bit lines to the logical addressused by the outside computer system is stored in a row CAM 43.

[0020] There are additional rows and columns of storage cells in array11 beyond those needed to store the number of bits for which the memorywas designed. These spares can be used to replace the defective memorycells by changing the mapping stored in CAMs 42 and 43. In oneembodiment of the present invention, each time memory 10 is powered up,a controller 40 loads the CAMs with default values and tests the memoryarray to determine if any bad rows or columns exist. If a bad row isfound, controller 40 alters the mapping in CAM 43 such that the bad rowis replaced by one of the spare rows. Similarly, if a bad column isfound, the mapping in CAM 42 is altered such that the bad column isreplaced by one of the spare columns.

[0021] As noted above, test speed has been a problem in prior art memorydesigns. The present invention overcomes the speed limitations byproviding the testing function on the memory chip itself and by using ahighly parallel testing strategy. During the testing phase, controller40 stores and retrieves test values from entire rows. In general, thesense amplifier block 21 includes a register having one bit per bit linethat latches the value read from the currently selected row. The valuesin this register may be connected back to the bit lines during thetesting operation. Hence, many words can be tested in a singlewrite/read operation. For example, in a 1 Gbyte embodiment of thepresent invention, each row includes 72 Kbits of storage.

[0022] Furthermore, the speed with which the controller can perform atest cycle on a row is not limited by the speed of the external bus thatconnects the memory to the central processing unit (CPU) in the computersystem. Accordingly, the present invention can run at higher internalclock speeds during testing, and hence, provide even faster memorytesting.

[0023] Finally, memory 10 is typically one of several memory blocks on amemory chip. For example, the 1 Gbyte embodiment of the presentinvention described above includes 4 such blocks. During testing, eachblock is isolated from the others and can perform tests in parallel withthe other blocks. The combination of the high degree of parallelprocessing and increased internal speed allow the present invention totest memory cells at the rate sufficient to identify even intermittentlyfailing cells prior to bringing the memory on line. The memory can thenbe configured to prevent data storage in the bad cells.

[0024] In the preferred embodiment of the present invention, the actualdata stored in the storage array is encoded via an error correction codeto further improve the reliability of the memory. Refer now to FIG. 2,which is a block diagram of a memory 50 according to the presentinvention that utilizes an error correcting code. To simplify thefollowing discussion, those elements of memory 50 that serve the samefunctions as elements shown in FIG. 1 have been given the same numericaldesignations and are assumed to perform the same functions unless thetext indicates otherwise.

[0025] In memory 50, each word also includes a number of errorcorrecting bits that are stored with the word. The error correcting bitsare added to the data word by an error correcting code (ECC) generator30 prior to storing the combined data and error correcting bits instorage array 11. Hence, each word actually occupies N storage cells,where N>N_(D).

[0026] The error correcting bits serve two functions. First, the errorcorrecting bits allow some bit errors to be corrected by errorcorrection circuit 31. In the preferred embodiment of the presentinvention, sufficient error correcting bits are provided to allow allone-bit errors to be corrected and all two-bit errors to be detected.Error correcting codes that provide this type of functionality are wellknown to those in the art, and hence, will not be discussed in detail

[0027] Second, the error correcting bits allow the present invention todetermine which bits failed. This information is sent to controller 40by error correcting circuit 31. Controller 40 keeps track of thelocations of the errors to determine if one or more rows or columns ofstorage cells, or the electronics associated therewith are failing. Whencontroller 40 determines that a particular column or row is failing,controller 40 substitutes a spare column or row included in storagearray 11 for the failing column or row by altering the appropriatemapping in either CAM 42 or 43. In effect, memory 50 is in a test modeeven when it is operating to store data.

[0028] Column replacements are much more costly, both in terms of downtime for the memory and hardware, than row replacements. A rowreplacement can be accomplished in a single read-write cycle, since allof the bits of the old row are available at the same time and all of thebits of the new row can be written at once using the register in thesense amplifier block discussed above. In memories based on conventionalDRAMs, the row replacement can be carried out as part of the normalrefresh cycle.

[0029] The replacement of a column is somewhat more complicated, sinceeach row in the defective column must be read and rewritten such thateach cell in the defective row is replaced by a corresponding cell inone of the spare columns. During such a re-configuration involving a rowreplacement, the memory may not be available for a significant period oftime. During the time a column is being replaced, the present inventionstalls the central processor by making use of the serial master (SM) busthat is incorporated in many processor designs for out of bandcommunications between memory and the CPU.

[0030] In addition, column replacements require the two cross-connectswitches described above; while row replacements require only theregister in the sense amplifier block. To reduce the complexity of theseswitches, the present invention utilizes a more restrictive form ofcolumn replacement. In the preferred embodiment of the presentinvention, each row can be replaced by only a limited number of theavailable spare rows. For example, a row might be defined to have 2spare columns of memory cells between each two bytes on the row. Thesespares would service the bytes immediately adjacent to the spares;hence, the cross-connect switch would need only 32 switches forconnecting these two bytes to the two spares. In contrast, 288 switchingelements would be needed if all possible columns are to be used in anybit position. Hence, this restriction reduces the number of switchingelements in the cross-connect switches, since a switching element isonly needed between the lines that could potentially be connected to oneanother.

[0031] If the number of data bits per word is large compared to thenumber of bits in the address, it is more efficient to use a single bitCAM 60 for the spares than to replace an entire row when one bit in therow is defective. In embodiments of the present invention that utilizesuch single bit replacements, the data and bit location are stored inCAM 60 which inserts the data bit into the outbound data word with theaid of a multiplexer 61. Data for the defective bit is copied into CAM60 at the same time the data for the remaining bits is stored in storagearray 11. The specific bits that are stored in CAM 60 are determined bycontroller 40. To simplify the drawing, the connections betweencontroller 40 and CAM 60 have been omitted.

[0032] In general, there will be a plurality of storage arrays such asstorage array 11 that share the same cross-connect switches, senseamplifiers, etc. For each such array, column CAM will provide onemapping of the columns to the bits of the data words. The identity ofthe block currently connected to the sense amplifiers, etc. isdetermined by the row address. The blocks may be viewed as apartitioning of the rows into a sequence of blocks that share the samesense amplifier block; hence, the loss of a sense amplifier may stillrequire a column replacement. Each block, however, has its own bit linesthat operate independently of the bit lines of the other blocks; hence,a break in a bit line can be accommodated by mapping the rows to otherblocks rather than replacing an entire column.

[0033] As noted above, column replacements are quite costly compared torow replacements; hence, it should also be noted that systems that donot use column replacements may be constructed without deviating fromthe teachings of the present invention. In such systems, the column CAMand much of the cross-connect hardware can be eliminated. The column CAMallows one to replace one column of storage cells with another column ofstorage cells. It provides the greatest benefit when one sense amplifierfails. If there are sufficient error correcting bits to correct forseveral bits in each word being in error, then the error correctingcircuitry can cover the loss of the column without losing the entirememory array. Alternately, spare sense amplifiers may be included ineach block of sense amplifiers together with the gates needed to inserta spare in place of a failed amplifier.

[0034] In the above-described embodiments of the present invention, theerror correction circuit 31 communicates the identity of the bits thatare found to be erroneous to the controller as the various data wordsare delivered to the CPU. The time to communicate this information andhave the controller store it can be longer than a memory cycle.Accordingly, some error events will be lost in the sense that thecontroller will not record and act on the events even though the errorcorrection circuit corrected the errors. This situation is most likelywhen the CPU is executing a section of code that concentrates heavily onmemory accesses in one region of the memory and that region has a weakstorage cell. In principle, this situation can lead to the loss ofinformation about a second weak storage cell in another region of memorythat is not being accessed as often, because the controller misses theerror report for the second weak storage cell because of an overload oferror reports for the first weak storage cell.

[0035] One method for avoiding such lost reports is to utilize a bufferin error correction circuit 31 that accumulates errors by the address atwhich the error occurred. Such a buffer can be constructed in a manneranalogous to a CAM. A CAM stores a data record associated with a givenaddress. Each time a request is made for data at a given address, theCAM recovers the record for that address and passes along the datarecord. In the preferred embodiment of the present invention, a device,referred to as a content addressable counter (CAC) is utilized to storethe error records prior to transferring the same to the controller. ACAC stores one record for each address; however, the contents of therecord are sets of counters corresponding to the various single biterrors that can be observed at any address. For example, if an error isseen in the second bit of a row at a given address, the CAC is queriedto see if it has an entry for that address. If so, the second counter inthe record is incremented. If no such record exists, the CAC assigns thenext free record to that address and initializes the counters to zero.If no free records exist, the CAC has an overflow condition, and thecontents of the CAC are sent to the controller for processing. All ofthe records are then marked for replacement and the memory proceedsaccordingly. If any given counter reaches its maximum value, it is notincremented further.

[0036] The CAC can be part of the error correction circuit or thecontroller or a separate buffer located between the two. In thepreferred embodiment of the present invention, the CAC is included inthe controller if such a buffer is utilized.

[0037] While the present invention has been described in terms of amemory that reconfigures itself during operation to provide a memory ofa predetermined size that is error free, the present invention may alsobe utilized to provide a memory that has a size that is communicated tothe central processor at start up. In such embodiments, the presentinvention uses all of the spare rows to provide data storage duringnormal operation. At start up, controller 40 tests the memory toidentify any bad rows. The remaining rows are mapped to memoryaddresses. The maximum number of words that are available are thencommunicated by controller 40 to the CPU over the SM bus.

[0038] Such embodiments of the present invention have the advantage offailing “gracefully” as more and more memory cells become inoperativewith age. In general, data processing systems have some minimum RAMrequirement. Most computer systems are sold with significantly more RAMthan the minimum. RAM above this minimum improves the efficiency andstability of the system. For example, part of this additional RAM isused as a disk cache to reduce the delays associated with moving datafrom disk to memory. In conventional memory systems, a block of badmemory in the middle of the RAM will cause the memory to fail if anaddress in the bad block is used. Hence, even if the system is smartenough to spot the bad RAM and reduce the available RAM size such thataddresses above the bad address are used, the system will have lost halfits memory. In effect, the system has to throw out the good RAM that isabove the bad block of memory since the operating system assumes thatmemory is contiguous. In contrast, the present invention “moves” the badaddresses to the back of the memory leaving all of the good memory inwhat appears to be a continuous block. Hence, even if a memory accordingto the present invention runs out of spare rows, it will always be ableto use the good rows.

[0039] As noted above, the internal organization of a memory accordingto the preferred embodiment of the present invention provides for muchfaster testing than is available in conventional memories. Conventionalmemories are tested by storing and reading data across the memory busbetween the central processor and the memory. Hence, the data rates arelimited by the width and speed of the system bus which is typically lessthan or equal to 64 bits wide and which runs at approximately 100 MHz.Accordingly, periodic exhaustive or even thorough testing of a memoryfor cells to detect intermittent failures is not possible in prior artmemory designs when memory size begins to exceed 100 Mbytes.

[0040] As a result of these limitations, memories are tested thoroughlyonce after fabrication and repairs made to defective parts, if possible.This process requires specialized test equipment and long testing times.Both of these factors increase the cost of the final memory. Inaddition, even with specialized test equipment, the time available fortesting does not permit tests to be run over a full range of possibleoperating conditions. For example, a part that does not operate at thehighest possible clock frequency may operate satisfactorily at a lowerclock frequency, and hence, be useable. The cost of identifying suchparts, however, precludes their reclamation and sale. In any event, oncememory passes, it is not thoroughly tested again until a system in whichit is located fails and diagnostic procedures are instituted todetermine the cause of failure.

[0041] As noted above, the present invention overcomes thesedifficulties by providing a fast highly parallel system of memorytesting on the memory chip. This aspect of the present invention willnow be explained in more detail with the aid of FIG. 3, which is a blockdiagram of a memory 100 according to the present invention. Memory 100differs from memory 10 discussed above in two significant aspects.First, memory 100 is constructed from a plurality of memory banks.Exemplary memory banks are shown at 101 and 102. Each memory bank issimilar to that shown in FIG. 2. For example, memory bank 101 includes acontroller 105, row and columns CAMs 109, ECC generator 108, storagearray 111, and ECC correction circuit 107. The memory banks connect to abus 104, which includes the various signal lines used to connect thememory to the external memory bus. A memory block interface 103 is usedto connect, or disconnect, memory block 101 from the system bus 104.Hence, controller 105 can run tests on storage array 111 at the sametime controller 205 in memory block 102 is running tests on the storagearray in that memory block. Accordingly, the test time is reduced by afactor equal to the number of memory blocks in the memory.

[0042] In addition to the improvements provided by dividing the memoryinto blocks for testing, the present invention also takes advantage ofthe higher speeds with which the internal buses in the memory operate.In general, the internal buses will support clock rates that are higherthan the system bus clock rate because of the short distances betweencomponents within the memory. In the preferred embodiment of the presentinvention, interface 103 includes a phase locked frequency generatorthat generates the clock signals used during testing from a slower clocksignal on bus 104. In the preferred embodiment of the present invention,a number of different clock rates are tested to determine the highestfrequency at which each memory block will function.

[0043] Finally, as noted above, the storage arrays utilize much widerrows than those used in conventional storage arrays. In one embodimentof the present invention of the type shown in FIG. 2, each row includes72 Kbits and there are 4 memory blocks providing a total of 1 Gbyte ofstorage. Hence, this embodiment reads and writes storage words that areeffectively 288 Kbits long. During testing all 4 blocks read and writein parallel. During normal operation, 64 bit words are read and writtenfrom the appropriate block in the memory as determined by the addressassociated with the word. The row assigned to that address is read inparallel providing 1024 64 bit words together with 8 ECC bits for each64 bit word. This data is stored in a register that is part of the senseamplifier array. The appropriate 72 columns are directed to the ECCcircuitry by a cross-connect switch as described above with reference tomemory 10 discussed above. It should be noted that after reading out therequested word, the remaining words are still available in the outputregister. Hence, if a second read request, directed to another word inthis row is received prior to the contents of this register beingaltered, that request can be serviced in a fraction of the access timerequired to provide the first word from the row.

[0044] A write operation is somewhat more complicated. To write data toone of the positions in the row, the entire row is first read out intothe output register discussed above. The new data, together with itsadditional ECC bits, is then written into the appropriate location inthat register, and the entire row is written back into the storagearray. The same cross-connect switch used to reconfigure the memory canbe used to direct the 64 bits being written to the appropriate locationin the register.

[0045] Since the present invention can perform an extensive memory testduring the power up cycle of a computer, the expensive and timeconsuming memory testing normally performed on the production line canbe omitted. In the preferred embodiment of the present invention, thememory is tested during burn-in at a number of different clock speeds.The results of the testing can be utilized to sort the memory byperformance characteristics. For example, memory chips that operate overa wider range of temperature and/or frequency can be sorted and sold fora premium.

[0046] The embodiments discussed above utilize a CAM to map the physicaladdresses within the memory chip, i.e., row and columns in the storagearray, to the logical addresses utilized by the computer system in whichthe memory functions. However, it will be obvious to those skilled inthe art from the preceding discussion that any form of mapping circuitcan be utilized for this function. In addition, the mapping circuit caninclude some form of non-volatile memory such as EEPROM or FLASH inwhich the address mapping is stored when power is turned off. Suchstorage allows the memory to be configured once during burn in. Thistype of memory would mimic conventional memory, and hence, provideupward compatibility in systems that do not test memory prior tooperation.

[0047] The above-described embodiments of the present invention storethe error correcting bits on the same row as the data bits. However, itwill be obvious to those skilled in the art from the precedingdiscussion that these bits can be stored in a separate storage arraywhich is accessed via row select circuitry or directly via the wordaddress. In the later case, the error correcting code storage space isnot reconfigurable; however, savings in CAM hardware are achieved.

[0048] The above-described embodiments of the present invention storeone bit per memory storage cell. That is, the data values read from thebit lines are either 1 or 0. However, the present invention may also beutilized in “multi-level” memories in which each storage cell stores aplurality of bits in the form of an analog value that is decoded by thesense amplifiers which now include some form of analog-to-digitalconverter. In this case, the single data values run from 0 to V, whereV>1.

[0049] The above-described embodiments of the present invention utilizethe error-correcting code hardware both to correct damaged data and todetect memory cells that have failed or have a high error rate, andhence, should not be used. In very high-speed memories, theerror-correcting code hardware can slow down the memory, since evenuncorrupted data must wait for the ECC hardware to determine if a dataword is in error. Embodiments of the present invention that avoid thesedelays while allowing reconfiguration can also be constructed withoutdeviating from the teachings of the present invention.

[0050] Refer now to FIG. 4, which is a block diagram of a memory 300according to the present invention connected to a bus 320 that is usedto transfer the data to a central processor or the like. Memory 300includes a bus interface 306 that sends and receives data on bus 320. Anerror-correcting code generating circuit 301 inserts the ECC bits intodata words stored in storage array 302. The physical location of thestorage locations corresponding to any given address are stored in therow/column CAMs shown at 304. Memory 300 operates substantially the sameas the memories according to the present invention discussed above withrespect to storing in storage array 302 and fetching data therefrom. Therows and columns selected by CAM 304 are determined by the addresspresented on bus 320 and the data stored in the CAMs by controller 305.The connections between bus interface 306 and CAM 304 have been omittedto simplify the drawing.

[0051] Memory 300 differs from the embodiments of the present inventiondescribed above in that data retrieved from storage array 302 isimmediately provided both to bus interface 306 and ECC correctioncircuit 303. This requires that the error correcting scheme utilize acode in which the data bits are augmented by a number of “errorcorrecting bits” such that the data bits are immediately accessible.

[0052] If a data error is detected by ECC correction circuit 303, thedata indicating the corrected data word and the bits that were in errorare forwarded to controller 305 in a manner analogous to that discussedabove with respect to the embodiments of the present invention that areshown in FIGS. 2 and 3. This data is used to identify storage locationsthat are defective so that controller 305 can map the correspondingaddresses to non-defective rows and columns of storage array 302. Thebackground data collection and remapping of the CAMs is carried out inan analogous manner as that described above.

[0053] If ECC correcting circuit 303 detects a data error there arethree possible actions depending on the particular embodiment of thepresent invention being utilized. First, controller 305 could just allowthe bad data to be delivered to the device on the other end of bus 320.Such an embodiment would be no worse than the prior art memory systemscurrently being used in data processing systems.

[0054] Second, the error correcting bits can also be placed on the bus.In this embodiment, the receiving device is assumed to also have an ECCcorrecting circuit that can at least detect the presence of an error inthe delivered data word. The recipient can then correct the data orre-request the data if the recipient has only partial error correctingcapability.

[0055] Third, controller 305 can signal an error and cause the intendedrecipient of the data to delay reading the bus. The error signal cancause the recipient resubmit the read request or at least wait one buscycle before reading the data. During the resulting delay, controller305 loads bus interface 306 with the corrected data, and hence, therecipient receives the corrected data after a one memory cycle delay.Since erroneous data is assumed to occur relatively infrequently, suchdelays are of little consequence in the overall speed of the dataprocessing system.

[0056] The error signal can be generated on bus 320 by controller 305 insystems that provide for a bus fault signal or detect bus faults. Inanother embodiment of the present invention, controller 320 initiates aninterrupt whose processing software causes the data to be re-requested.Alternatively, the signal can cause the cache associated with the dataprocessor to be flushed, which will also cause a re-read of the data onthe next cache miss at the address in question. Finally, a separate busline can be provided for signaling such errors.

[0057] Various modifications to the present invention will becomeapparent to those skilled in the art from the foregoing description andaccompanying drawings. Accordingly, the present invention is to belimited solely by the scope of the following claims.

What is claimed is:
 1. A reconfigurable memory comprising: M bit lines,where M>1; a plurality of row lines; an array of memory storage cells,each memory storage cell storing a data value and comprising circuitryfor coupling that data value to one of said bit lines in response to arow control signal on one of said row lines; a row select circuit forgenerating said row control signal on one of said row lines in responseto a row address being coupled to said row select circuit, said rowselect circuit comprising a memory for storing a mapping of said rowaddresses to said row lines, said mapping determining which of said rowlines is selected for each possible value of said row address; acontroller for determining that one of said memory cells is defectiveand for altering said mapping if one of said memory cells is determinedto be defective; an error correcting circuit for detecting errors indata words, said error correcting circuit generating an error data wordfrom N data values coupled thereto, wherein N is less than or equal toM, said error data word indicating which of said N data values, if any,was erroneous; a bus interface circuit for coupling values stored insaid array of memory storage cells to a bus; and a word assembly circuitfor connecting N of said M bit lines to said error correcting circuitand N_(D) of said M bit lines to said bus interface circuit, whereinN_(D) is less than or equal to N, and said control circuit alters saidmapping in said row select circuit in response to said error data wordsindicating that one of said memory storage cells is defective.
 2. Thememory of claim 1 wherein said controller further comprises a read abortcircuit for generating an abort signal indicating that one of saidvalues coupled by said bus interface is in error.
 3. The memory of claim2 wherein said abort signal causes a device connected to said bus todelay reading data on said bus for a time sufficient to allow saidcontroller to couple corrected values to said bus interface circuit. 4.The memory of claim 3 wherein said abort signal causes a fault to bedetected on said bus by a device connected to said bus.